1. Field of the Invention
The present invention relates to a level converter for converting a power source voltage level of an ECL (emitter-coupled logic) circuit to a power source voltage level of a TTL (transistor-transistor logic) circuit.
2. Description of the Related Art
A level converter is required to operate a TTL circuit having a positive power source as a power source voltage using a signal of an ECL-circuit level having a negative power source as a power source voltage.
For example, an ECL-level input signal is input to the bases of a pair of differential transistors. The collector of one transistor of the pair of differential transistors is connected to a ground voltage GND. A power source voltage VCC is applied to the collector of the other transistor through a level-converting resistor. The collector current of the other transistor is controlled by the ECL-level input signal, and a voltage determined by the voltage drop of the level converting resistor applied with the power source voltage VCC is output as a signal level for the TTL circuit.
Since a TTL circuit is a circuit using a saturation region of a transistor, it is disadvantage to a high-speed operation. In order to obtain the high-speed operation, a clamp circuit for controlling saturation of transistors constituting the TTL circuit is frequently incorporated in the TTL circuit.
When a clamp voltage required for a clamp circuit in the TTL circuit is generated from a level converter, a clamp level can be arbitrarily set by the level converter. For this reason, a resistor connected in series with a level-converting resistor connected to the collectors of the pair of differential transistors receiving an ECL-level signal is arranged, and a power source voltage VCC supplied to the transistors is divided by the resistors, thereby obtaining a clamp level.
However, the method of obtaining the clamp level with the above arrangement has the following drawbacks.
First, a resistor component for defining a time constant of charging/discharging of a capacitance C parasitized in a TTL-level output node is increased by the level-converting resistor and the resistor connected in series therewith, thereby causing a level-converting speed to be decreased.
Second, a clamp level determined by dividing the power source voltage VCC by the level-converting resistor and the resistor connected in series therewith is varied by an influence of a change in voltage due to the level-converting resistor for obtaining a TTL level.